1. Field of the Invention
The present invention relates generally to data transmission and reception and specifically to data transmission and reception in an Interconnect Chip.
2. Description of Background Art
The speed of data read and write within an integrated circuit is affected in part by the cost (in time) of accessing the status of entries in a direct memory access (DMA) list. Each read of the DMA list over a slow connection by a host processor adds a delay in processing, yet to work correctly the host processor needs to know the current status of the DMA list.
DMA occurs when a hardware device transfers data from an input/output (I/O) port of the hardware device to and/or from system memory without direct host processor interaction. DMA lists tell the I/O device which memory locations and ranges are to be transferred, and in which direction. The DMA list is accessed via a DMA head pointer. In a conventional DMA system, head pointer information is read from the I/O device by the host processor, which introduces latency.
In a conventional DMA system, the host processor accesses the DMA head pointer to determine which location in the DMA list is to be processed next. Once the processing of the next item in the DMA list is complete, the conventional approach is to have the host processor read the DMA head pointer from the I/O device to determine if the head pointer has changed. Either the host processor polls the I/O device, or the I/O device interrupts the host processor to be read. In either case, access to the I/O device is slow, and the host processor is stalled until the read of the head pointer is complete.
The typical process for determining memory locations and memory status begins when a host processor constructs a DMA list. The DMA list is then written either directly into the I/O device using programmed input/output (PIO) instructions or into system memory accessed via a head pointer that is written into the I/O device. The I/O device then directly accesses the information in the list by fetching DMA through the DMA head pointer. At this point, the I/O device registers containing the DMA head pointer can be read by the host processor, pointing it to the next item to be processed.
Alternatively, the host processor can access the entries for the DMA list by reading status words directly from system memory. This method has an overhead cost for accessing the status words and determining whether the I/O device or the host processor changed a memory location last.
What is needed are methods and systems for eliminating the delay in conventional DMA.